pst-circ (28apr21)

git-svn-id: svn://tug.org/texlive/trunk@59017 c570f23f-e606-0410-a88d-b1316a301751

1 files changed, 227 insertions, 151 deletions

diff --git a/Master/texmf-dist/tex/generic/pst-circ/pst-circ.tex b/Master/texmf-dist/tex/generic/pst-circ/pst-circ.tex
index 770e2ff8422..d13be6321d3 100644
--- a/Master/texmf-dist/tex/generic/pst-circ/pst-circ.tex
+++ b/Master/texmf-dist/tex/generic/pst-circ/pst-circ.tex
@@ -26,8 +26,8 @@
 \ifx\PSTXKeyLoaded\endinput   \else\input pst-xkey \fi
 \ifx\PSTMultidoLoaded\endinput\else\input multido.tex\fi
 %
-\def\fileversion{2.17}
-\def\filedate{2020/05/26}
+\def\fileversion{2.18}
+\def\filedate{2021/04/28}
 \message{`pst-circ' v\fileversion (hv)}
 %
 \edef\PstAtCode{\the\catcode`\@}
@@ -57,6 +57,8 @@
 \def\pst@Ttype@PNP{PNP}
 \def\pst@Ttype@NPN{NPN}
 \def\pst@Ttype@FET{FET}
+\def\pst@Ttype@JFET{JFET}
+\def\pst@Ttype@IGBT{IGBT}
 \def\pst@Ttype@NMOS{NMOS}
 \def\pst@Ttype@PMOS{PMOS}
 %
@@ -150,8 +152,13 @@
 \define@key[psset]{pst-circ}{transistoriemitterlabel}[]{\def\psk@labeltransistoriemitter{#1}}
 \define@key[psset]{pst-circ}{FETchanneltype}{\def\psk@FETchanneltype{#1}}% Ted 2007-10-15
 \define@boolkey[psset]{pst-circ}[Pst@]{FETmemory}[true]{}
+\define@boolkey[psset]{pst-circ}[Pst@]{DMOSFET}[false]{}
 \define@key[psset]{pst-circ}{transistortype}[NPN]{%
   \def\psk@Ttype{#1}%
+  \ifx\psk@Ttype\pst@Ttype@JFET \Pst@transistorcirclefalse\fi
+  \ifx\psk@Ttype\pst@Ttype@NMOS \Pst@transistorcirclefalse\fi
+  \ifx\psk@Ttype\pst@Ttype@PMOS \Pst@transistorcirclefalse\fi
+  \ifx\psk@Ttype\pst@Ttype@IGBT \Pst@transistorcirclefalse\fi
   \ifx\psk@Ttype\pst@Ttype@FET \Pst@transistorcirclefalse\fi}
 \newdimen\Pst@basesep
 \define@key[psset]{pst-circ}{basesep}[0]{\pst@getlength{#1}\Pst@basesep}
@@ -861,6 +868,7 @@
   transistoricollectorlabel={},transistoriemitterlabel={},
   transistortype=NPN,TRot=0,%
   FETmemory=false,						% atosch
+  DMOSFET=false, % MOSFET type: D or E
   primarylabel={},secondarylabel={},transformeriprimary=false,transformerisecondary=false,
   transformeriprimarylabel={},transformerisecondarylabel={},
   tripolestyle=normal,variable=false,
@@ -1165,7 +1173,7 @@
 %
 \def\transistor@ii(#1)#2#3{% with one node, the base
   \pst@killglue%
-  \ifPst@temp\pnode(#1){TBaseNode}%
+  \ifPst@temp\pnode(#1){TBaseNode}% Base
   \else
     \pst@getcoor{#1}\pst@tempA%
     \pnode(!
@@ -1174,157 +1182,225 @@
       /basesep \Pst@basesep\space \pst@number\psxunit div def
       XB basesep \Pst@TRot\space cos mul add
       YB basesep \Pst@TRot\space sin mul add){TBaseNode}% base node
-  \fi
+  \fi % Base
   \rput[c]{\Pst@TRot}(!
-      \pst@tempA /YB exch \pst@number\psyunit div def
-      /XB exch \pst@number\psxunit div def
-      /basesep \Pst@basesep\space \pst@number\psxunit div def
-      XB basesep \Pst@TRot\space cos mul add
-      YB basesep \Pst@TRot\space sin mul add){%
-    \ifdim180pt=\Pst@TRot pt\relax
-      \ifPst@transistorcircle\pscircle(0.3,0){0.7}\fi
-      \ifx\psk@Ttype\pst@Ttype@NPN\relax
-          \ifPst@transistorinvert
-            \pnode(0.5,-0.5){#2}%
-            \pnode(0.5,0.5){#3}%
-          \else
-            \pnode(0.5,-0.5){#3}%
-            \pnode(0.5,0.5){#2}%
-          \fi
-          \psline[linewidth=4\pslinewidth,arrows=-](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-          \psline[arrowinset=0,arrowsize=8\pslinewidth,arrows=->](#2)(TBaseNode)(#3)%
-      \else
-        \ifx\psk@Ttype\pst@Ttype@PNP\relax
-	  \ifPst@transistorinvert
-            \pnode(0.5,-0.5){#2}\pnode(0.5,0.5){#3}%
-          \else
-            \pnode(0.5,-0.5){#3}\pnode(0.5,0.5){#2}%
-          \fi
-          \psline[linewidth=4\pslinewidth,arrows=-](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-          \psline[arrowinset=0,arrowsize=8\pslinewidth,arrows=->,dimen=middle](0.5,-0.5)(TBaseNode)%
-          \psline(0.5,0.5)(TBaseNode)
-        \else%  FET 
-				\ifx\psk@Ttype\pst@Ttype@FET\relax%
-					\ifPst@transistorinvert\pnode(0.75,-0.5){#2}\else\pnode(0.75,-0.5){#3}\fi%
-        			\ifPst@transistorinvert\pnode(0.75,0.5){#3}\else\pnode(0.75,0.5){#2}\fi%
-				    % Main drawings
-				    \psline[arrows=-](0.75,0.5)(0.2,0.5)
-                    \psline[linestyle=dashed,dash=8pt 3pt,arrows=-](0.2,0.6)(0.2,-0.6)
-                    \psline[arrows=-](0.2,-0.5)(0.75,-0.5)%
-                    \ifPst@FETmemory% atosch
-                    	\psline[arrows=-,linewidth=\psk@I@width](-0.15,0.5)(-0.15,-0.5)%
-                  	\fi%
-                  	\psline[arrows=-,linewidth=\psk@I@width](TBaseNode|0,0.5)(TBaseNode|0,-0.5)%
-                    \ifx\psk@FETchanneltype\pst@FETchanneltype@P\relax% Ted 2007-10-15
-                		\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.2,0)(0.75,0)%
-						\ifPst@transistorinvert
-        					\qdisk(#3){1.5pt}\psline[origin={#3}]{-}(0,-0.5)%
-						\else
-							\qdisk(#3){1.5pt}\psline[origin={#3}]{-}(0,0.5)%
-						\fi
-              		\else%
-              			\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.2,0)(0.75,0)%
-						\ifPst@transistorinvert
-        					\qdisk(#2){1.5pt}\psline[origin={#2}]{-}(0,0.5)%
-						\else
-							\qdisk(#2){1.5pt}\psline[origin={#2}]{-}(0,-0.5)%
-						\fi
-             		\fi%
-				\else % NMOS or PMOS
-					\ifPst@transistorinvert\pnode(0.75,-0.4){#2}\else\pnode(0.75,-0.4){#3}\fi%
-        			\ifPst@transistorinvert\pnode(0.75,0.4){#3}\else\pnode(0.75,0.4){#2}\fi%
-					% Main drawings
-    				\psline[arrows=-](0.75,0.4)(0.15,0.4)
-                    \psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6)
-                    \psline[arrows=-](0.75,-0.4)(0.15,-0.4)%
-					 \ifx\psk@Ttype\pst@Ttype@NMOS\relax%
-					 	\ifPst@transistorinvert
-        					\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0.4)(0.75,0.4)%
-						\else
-							\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,-0.4)(0.75,-0.4)%
-						\fi
-						\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-					\else
-						\ifPst@transistorinvert
-        					\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,0.4)(0.75,0.4)%
-						\else
-							\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,-0.4)(0.75,-0.4)%
-						\fi
-						\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-					\fi
-				\fi
-        	\fi %
-      	\fi%
-    \else%
-    	\ifPst@transistorcircle\pscircle(0.3,0){0.7}\fi
-		\ifx\psk@Ttype\pst@Ttype@FET\relax%
-			\ifPst@transistorinvert\pnode(0.65,0.5){#2}\else\pnode(0.65,0.5){#3}\fi%
-        	\ifPst@transistorinvert\pnode(0.65,-0.5){#3}\else\pnode(0.65,-0.5){#2}\fi%
-			% FET Main drawings
-		    \psline[arrows=-](0.65,0.5)(0.15,0.5) % upper line
-            \psline[linestyle=dashed,dash=8pt 3pt,arrows=-](0.15,0.6)(0.15,-0.6) % gate
-            \psline[arrows=-](0.15,-0.5)(0.65,-0.5)% lower line
-            \ifPst@FETmemory% atosch
-            	\psline[arrows=-,linewidth=\psk@I@width](-0.15,0.5)(-0.15,-0.5)%
-          	\fi%
-          	\psline[arrows=-,linewidth=\psk@I@width](TBaseNode|0,0.5)(TBaseNode|0,-0.5)%
-            \ifx\psk@FETchanneltype\pst@FETchanneltype@P\relax% Ted 2007-10-15
-        		\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0)(0.65,0)%
-				\qdisk(#3){1.5pt}\psline[origin={#3}]{-}(0,-0.5)%
-      		\else%
-      			\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,0)(0.65,0)%
-				\qdisk(#2){1.5pt}\psline[origin={#2}]{-}(0,0.5)%
-     		\fi%
-		\else
-			\ifx\psk@Ttype\pst@Ttype@NMOS\relax%
-				% NMOS Main drawings
-				\psline[arrows=-](0.65,0.4)(0.15,0.4) % upper line
-                \psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6) % gate
-                \psline[arrows=-](0.65,-0.4)(0.15,-0.4)% lower line
-                \psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-        		\ifPst@transistorinvert\pnode(0.65,0.4){#2}\else\pnode(0.65,0.4){#3}\fi%
-        		\ifPst@transistorinvert\pnode(0.65,-0.4){#3}\else\pnode(0.65,-0.4){#2}\fi%
+    \pst@tempA /YB exch \pst@number\psyunit div def
+    /XB exch \pst@number\psxunit div def
+    /basesep \Pst@basesep\space \pst@number\psxunit div def
+    XB basesep \Pst@TRot\space cos mul add
+    YB basesep \Pst@TRot\space sin mul add){%
+		\ifdim180pt=\Pst@TRot pt\relax % rotate 180?
+			\ifPst@transistorcircle\pscircle(0.3,0){0.7}\fi % circle drawing
+			\ifx\psk@Ttype\pst@Ttype@NPN\relax % NPN
 				\ifPst@transistorinvert
-        			\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0.4)(0.65,0.4)%
+					\pnode(0.5,-0.5){#2}% Emitter
+					\pnode(0.5,0.5){#3}% Collector
 				\else
-					\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,-0.4)(0.65,-0.4)%
-				\fi
-			\else
-				\ifx\psk@Ttype\pst@Ttype@PMOS\relax%
-				% PMOS Main drawings
-    				\psline[arrows=-](0.65,0.4)(0.15,0.4) % upper line
-                    \psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6) % gate
-                    \psline[arrows=-](0.65,-0.4)(0.15,-0.4)% lower line
-                	\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-            		\ifPst@transistorinvert
-                           \pnode(0.65,0.4){#2}\pnode(0.65,-0.4){#3}
-                        \else
-                           \pnode(0.65,0.4){#3}\pnode(0.65,-0.4){#2}
-                        \fi%
-    			\ifPst@transistorinvert
-            		  \psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,0.4)(0.65,0.4)%
-    			\else
-    			  \psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,-0.4)(0.65,-0.4)%
-    			\fi
-		   \else % PNP or NPN
-	   		\ifPst@transistorinvert
-                          \pnode(0.5,0.5){#2}\pnode(0.5,-0.5){#3}%
-                	\else                  
-                          \pnode(0.5,0.5){#3}\pnode(0.5,-0.5){#2}%
-        		\fi
-    			\ifx\psk@Ttype\pst@Ttype@NPN\relax% % NPN
-			  \psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(TBaseNode)(#2)%
-			  \psline[arrows=-,linewidth=4\pslinewidth](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-			  \psline[arrows=-](0.5,0.5)(TBaseNode)(0.5,-0.5)%
-    			\else%	% PNP
-			  \psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(#3)(TBaseNode)%
-			  \psline[arrows=-,linewidth=4\pslinewidth](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
-			  \psline[arrows=-](0.5,0.5)(TBaseNode)(0.5,-0.5)%
-			\fi
-      		    \fi
-      		\fi
-		\fi
-   	\fi
+					\pnode(0.5,-0.5){#3}% Collector
+					\pnode(0.5,0.5){#2}% Emitter
+				\fi % no NPN
+				\psline[linewidth=4\pslinewidth,arrows=-](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+				\psline[arrowinset=0,arrowsize=8\pslinewidth,arrows=->](#2)(TBaseNode)(#3)%
+			\else % not NPN
+				\ifx\psk@Ttype\pst@Ttype@PNP\relax % PNP
+					\ifPst@transistorinvert
+						\pnode(0.5,-0.5){#2}\pnode(0.5,0.5){#3}% E C
+					\else
+		            	\pnode(0.5,-0.5){#3}\pnode(0.5,0.5){#2}% C E
+		          	\fi
+					\psline[linewidth=4\pslinewidth,arrows=-](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+					\psline[arrowinset=0,arrowsize=8\pslinewidth,arrows=->,dimen=middle](0.5,-0.5)(TBaseNode)%
+					\psline(0.5,0.5)(TBaseNode)
+				\else % not PNP
+					\ifx\psk@Ttype\pst@Ttype@FET\relax%  FET
+						\ifPst@transistorinvert\pnode(0.75,-0.5){#2}\else\pnode(0.75,-0.5){#3}\fi%
+						\ifPst@transistorinvert\pnode(0.75,0.5){#3}\else\pnode(0.75,0.5){#2}\fi%
+				    	% Main drawings
+			    		\psline[arrows=-](0.75,0.5)(0.2,0.5)
+                		\ifPst@DMOSFET% MOSFET type: D or E
+                   			\psline[linewidth=\psk@I@width,arrows=-](0.2,0.6)(0.2,-0.6)
+	                	\else
+    	               		\psline[linestyle=dashed,dash=8pt 3pt,arrows=-](0.2,0.6)(0.2,-0.6)
+        	        	\fi % MOSFET type: D or E
+            	    	\psline[arrows=-](0.2,-0.5)(0.75,-0.5)%
+                		\ifPst@FETmemory% atosch
+                   			\psline[arrows=-,linewidth=\psk@I@width](-0.15,0.5)(-0.15,-0.5)%
+	               		\fi%
+    	           		\psline[arrows=-,linewidth=\psk@I@width](TBaseNode|0,0.5)(TBaseNode|0,-0.5)%
+        	        	\ifx\psk@FETchanneltype\pst@FETchanneltype@P\relax% Ted 2007-10-15
+            	   			\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.2,0)(0.75,0)%
+							\ifPst@transistorinvert
+       							\qdisk(#3){1.5pt}\psline[origin={#3}]{-}(0,-0.5)%
+							\else
+								\qdisk(#3){1.5pt}\psline[origin={#3}]{-}(0,0.5)%
+							\fi
+        	   			\else%
+           					\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.2,0)(0.75,0)%
+							\ifPst@transistorinvert
+       							\qdisk(#2){1.5pt}\psline[origin={#2}]{-}(0,0.5)%
+							\else
+								\qdisk(#2){1.5pt}\psline[origin={#2}]{-}(0,-0.5)%
+							\fi
+    	       			\fi%
+					\else % JFET, NMOS or PMOS
+						\ifx\psk@Ttype\pst@Ttype@JFET\relax%  JFET
+							% JFET Main drawings
+							\psline[arrows=-](0.65,0.4)(0.15,0.4) % upper line
+							\psline[arrows=-](0.65,-0.4)(0.15,-0.4)% lower line
+							\psline[arrows=-,linewidth=3\psk@I@width](0.15,0.6)(0.15,-0.6)% gate
+							\ifPst@transistorinvert\pnode(0.65,-0.4){#2}\else\pnode(0.65,-0.4){#3}\fi%
+							\ifPst@transistorinvert\pnode(0.65,0.4){#3}\else\pnode(0.65,0.4){#2}\fi%
+							\ifx\psk@FETchanneltype\pst@FETchanneltype@P
+								\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0.0)(-0.35,0.0)%
+							\else
+								\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(-0.35,0.0)(0.15,0.0)%
+							\fi
+						\else % IGBT, NMOS or PMOS
+							\ifx\psk@Ttype\pst@Ttype@IGBT\relax%  IGBT
+								% IGBT Main drawings
+								\ifPst@transistorinvert
+									\pnode(0.65,-0.5){#2}\pnode(0.65,0.5){#3}
+									\pnode(0.15,0.12){#3c}\pnode(0.15,-0.12){#2c}
+								\else
+									\pnode(0.65,-0.5){#3}\pnode(0.65,0.5){#2}
+									\pnode(0.15,-0.12){#3c}\pnode(0.15,0.12){#2c}
+								\fi%
+								\psline[linewidth=\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6)
+								\psline[arrows=-,linewidth=\psk@I@width](TBaseNode|0,0.5)(TBaseNode|0,-0.5)%
+								\psline[arrows=-](#3)(#3c)%
+								\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(#2c)(#2)%
+							\else % NMOS or PMOS
+								\ifPst@transistorinvert\pnode(0.75,-0.4){#2}\else\pnode(0.75,-0.4){#3}\fi%
+    			   				\ifPst@transistorinvert\pnode(0.75,0.4){#3}\else\pnode(0.75,0.4){#2}\fi%
+								% Main drawings
+   								\psline[arrows=-](0.75,0.4)(0.15,0.4)
+        	        			\psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6)
+            	    			\psline[arrows=-](0.75,-0.4)(0.15,-0.4)%
+								\ifx\psk@Ttype\pst@Ttype@NMOS\relax% NMOS?
+						 			\ifPst@transistorinvert
+       									\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0.4)(0.75,0.4)%
+									\else
+										\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,-0.4)(0.75,-0.4)%
+									\fi
+									\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+								\else % PMOS
+									\ifPst@transistorinvert
+	       								\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,0.4)(0.75,0.4)%
+									\else
+										\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,-0.4)(0.75,-0.4)%
+									\fi
+									\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+								\fi
+							\fi % NMOS or PMOS
+						\fi % IGBT, NMOS or PMOS
+					\fi % JFET, NMOS or PMOS
+       			\fi % PNP
+	   		\fi% NPN
+	    \else % not 180
+    		\ifPst@transistorcircle\pscircle(0.3,0){0.7}\fi
+			\ifx\psk@Ttype\pst@Ttype@FET\relax% FET
+				\ifPst@transistorinvert\pnode(0.65,0.5){#2}\else\pnode(0.65,0.5){#3}\fi%
+    	    	\ifPst@transistorinvert\pnode(0.65,-0.5){#3}\else\pnode(0.65,-0.5){#2}\fi%
+				% FET Main drawings
+			    \psline[arrows=-](0.65,0.5)(0.15,0.5) % upper line
+        	    \ifPst@DMOSFET% MOSFET type: D or E
+					\psline[linewidth=\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6)
+				\else
+					\psline[linestyle=dashed,dash=8pt 3pt,arrows=-](0.15,0.6)(0.15,-0.6)
+				\fi %
+            	\psline[arrows=-](0.15,-0.5)(0.65,-0.5)% lower line
+	            \ifPst@FETmemory% atosch
+    	        	\psline[arrows=-,linewidth=\psk@I@width](-0.15,0.5)(-0.15,-0.5)%
+        	  	\fi%
+	          	\psline[arrows=-,linewidth=\psk@I@width](TBaseNode|0,0.5)(TBaseNode|0,-0.5)%
+    	        \ifx\psk@FETchanneltype\pst@FETchanneltype@P\relax% Ted 2007-10-15
+        			\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0)(0.65,0)%
+					\qdisk(#3){1.5pt}\psline{-}(#3)(0.65,0.0)%
+	      		\else%
+    	  			\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,0)(0.65,0)%
+					\qdisk(#2){1.5pt}\psline{-}(#2)(0.65,0.0)%
+     			\fi%
+			\else % not FET
+				\ifx\psk@Ttype\pst@Ttype@NMOS\relax% NMOS
+					% NMOS Main drawings
+					\psline[arrows=-](0.65,0.4)(0.15,0.4) % upper line
+            	    \psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6) % gate
+                	\psline[arrows=-](0.65,-0.4)(0.15,-0.4)% lower line
+	                \psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+    	    		\ifPst@transistorinvert\pnode(0.65,0.4){#2}\else\pnode(0.65,0.4){#3}\fi%
+        			\ifPst@transistorinvert\pnode(0.65,-0.4){#3}\else\pnode(0.65,-0.4){#2}\fi%
+					\ifPst@transistorinvert
+        				\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0.4)(0.65,0.4)%
+					\else
+						\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,-0.4)(0.65,-0.4)%
+					\fi
+				\else % not NMOS
+					\ifx\psk@Ttype\pst@Ttype@PMOS\relax% PMOS
+						% PMOS Main drawings
+    					\psline[arrows=-](0.65,0.4)(0.15,0.4) % upper line
+            	        \psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6) % gate
+                	    \psline[arrows=-](0.65,-0.4)(0.15,-0.4)% lower line
+                		\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+	            		\ifPst@transistorinvert
+							\pnode(0.65,0.4){#2}\pnode(0.65,-0.4){#3}
+       	                \else
+							\pnode(0.65,0.4){#3}\pnode(0.65,-0.4){#2}
+               	        \fi%
+		    			\ifPst@transistorinvert
+							\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,0.4)(0.65,0.4)%
+						\else
+    			  			\psline[arrowinset=0,arrowsize=8\pslinewidth]{<-}(0.15,-0.4)(0.65,-0.4)%
+    					\fi
+		   			\else % not NMOS -> JFET, IGBT, PNP or NPN
+						\ifx\psk@Ttype\pst@Ttype@JFET\relax%  JFET
+							% JFET Main drawings
+							\psline[arrows=-](0.65,0.4)(0.15,0.4) % upper line
+							%\psline[linewidth=3\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6) % gate large
+							\psline[arrows=-](0.65,-0.4)(0.15,-0.4)% lower line
+							%\psline[arrows=-,linewidth=1.5\psk@I@width](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+							\psline[arrows=-,linewidth=3\psk@I@width](0.15,0.6)(0.15,-0.6)% gate
+							\ifPst@transistorinvert\pnode(0.65,0.4){#2}\else\pnode(0.65,0.4){#3}\fi%
+							\ifPst@transistorinvert\pnode(0.65,-0.4){#3}\else\pnode(0.65,-0.4){#2}\fi%
+							\ifx\psk@FETchanneltype\pst@FETchanneltype@P
+								\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(0.15,0.0)(-0.35,0.0)%
+							\else
+								\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(-0.35,0.0)(0.15,0.0)%
+							\fi
+						\else % IGBT, NPN or PNP
+							\ifx\psk@Ttype\pst@Ttype@IGBT\relax%  IGBT
+								% IGBT Main drawings
+								\ifPst@transistorinvert
+									\pnode(0.65,0.5){#2}\pnode(0.65,-0.5){#3}
+									\pnode(0.15,-0.12){#3c}\pnode(0.15,0.12){#2c}
+								\else
+									\pnode(0.65,0.5){#3}\pnode(0.65,-0.5){#2}
+									\pnode(0.15,0.12){#3c}\pnode(0.15,-0.12){#2c}
+								\fi%
+								\psline[linewidth=\psk@I@width,arrows=-](0.15,0.6)(0.15,-0.6)
+								\psline[arrows=-,linewidth=\psk@I@width](TBaseNode|0,0.5)(TBaseNode|0,-0.5)%
+								\psline[arrows=-](#3)(#3c)%
+								\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(#2c)(#2)%
+							\else % NPN or PNP
+						   		\ifPst@transistorinvert
+									\pnode(0.5,0.5){#2}\pnode(0.5,-0.5){#3}% E C
+								\else                  
+									\pnode(0.5,0.5){#3}\pnode(0.5,-0.5){#2}% C E
+								\fi
+								\ifx\psk@Ttype\pst@Ttype@NPN\relax% % NPN
+									\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(TBaseNode)(#2)%
+									\psline[arrows=-,linewidth=4\pslinewidth](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+									\psline[arrows=-](0.5,0.5)(TBaseNode)(0.5,-0.5)%
+								\else%	% PNP
+									\psline[arrowinset=0,arrowsize=8\pslinewidth]{->}(#3)(TBaseNode)%
+									\psline[arrows=-,linewidth=4\pslinewidth](TBaseNode|0,0.4)(TBaseNode|0,-0.4)%
+									\psline[arrows=-](0.5,0.5)(TBaseNode)(0.5,-0.5)%
+								\fi % NPN or PNP
+		      		    	\fi % IGBT
+	      		    	\fi % JFET
+       		    	\fi %JFET, PNP or NPN
+      			\fi % NMOS
+			\fi %FET
+   		\fi % 180
   }%
   \ifPst@temp\else\endgroup\fi%
   \ignorespaces%